Lecture 18: Function Calls & Machine Language

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1 Lecture 18: Function Calls & Machine Language
E85 Digital Design & Computer Engineering Lecture 18: Function Calls & Machine Language

2 Lecture 18 Function Calls Machine Language

3 Programming Building Blocks
Data-processing Instructions Conditional Execution Branches High-level Constructs: if/else statements for loops while loops arrays function calls

4 Function Calls Caller: calling function (in this case, main)
Callee: called function (in this case, sum) C Code void main() { int y; y = sum(42, 7); ... } int sum(int a, int b) return (a + b);

5 Function Conventions Caller: passes arguments to callee
jumps to callee

6 Function Conventions Caller: Callee: passes arguments to callee
jumps to callee Callee: performs the function returns result to caller returns to point of call must not overwrite registers or memory needed by caller

7 ARM Function Conventions
Call Function: branch and link BL Return from function: move the link register to PC: MOV PC, LR Arguments: R0-R3 Return value: R0

8 Function Calls C Code ARM Assembly Code
int main() { simple(); a = b + c; } void simple() { return; ARM Assembly Code 0x MAIN BL SIMPLE 0x ADD R4, R5, R6 ... 0x SIMPLE MOV PC, LR void means that simple doesn’t return a value

9 Function Calls C Code ARM Assembly Code BL branches to SIMPLE
int main() { simple(); a = b + c; } void simple() { return; ARM Assembly Code 0x MAIN BL SIMPLE 0x ADD R4, R5, R6 ... 0x SIMPLE MOV PC, LR BL branches to SIMPLE LR = PC + 4 = 0x MOV PC, LR makes PC = LR (the next instruction executed is at 0x )

10 Input Arguments and Return Value
ARM conventions: Argument values: R0 - R3 Return value: R0

11 Input Arguments and Return Value
C Code int main() { int y; ... y = diffofsums(2, 3, 4, 5); // 4 arguments } int diffofsums(int f, int g, int h, int i) int result; result = (f + g) - (h + i); return result; // return value

12 Input Arguments and Return Value
ARM Assembly Code ; R4 = y MAIN ... MOV R0, #2 ; argument 0 = 2 MOV R1, #3 ; argument 1 = 3 MOV R2, #4 ; argument 2 = 4 MOV R3, #5 ; argument 3 = 5 BL DIFFOFSUMS ; call function MOV R4, R0 ; y = returned value ; R4 = result DIFFOFSUMS ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 MOV PC, LR ; return to caller

13 Input Arguments and Return Value
ARM Assembly Code ; R4 = result DIFFOFSUMS ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 MOV PC, LR ; return to caller diffofsums overwrote 3 registers: R4, R8, R9 diffofsums can use stack to temporarily store registers

14 The Stack Memory used to temporarily save variables
Like stack of dishes, last-in-first-out (LIFO) queue Expands: uses more memory when more space needed Contracts: uses less memory when the space no longer needed

15 The Stack Grows down (from higher to lower memory addresses)
Stack pointer: SP points to top of the stack Stack expands by 2 words

16 How Functions use the Stack
Called functions must have no unintended side effects But diffofsums overwrites 3 registers: R4, R8, R9 ARM Assembly Code ; R4 = result DIFFOFSUMS ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 MOV PC, LR ; return to caller

17 Storing Register Values on the Stack
ARM Assembly Code ; R2 = result DIFFOFSUMS SUB SP, SP, #12 ; make space on stack for 3 registers STR R4, [SP, 8] ; save R4 on stack STR R8, [SP, #4] ; save R8 on stack STR R9, [SP] ; save R9 on stack ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 LDR R9, [SP] ; restore R9 from stack LDR R8, [SP, #4] ; restore R8 from stack LDR R4, [SP, #8] ; restore R4 from stack ADD SP, SP, #12 ; deallocate stack space MOV PC, LR ; return to caller

18 The Stack during diffofsums Call
Before call During call After call

19 Registers Preserved Nonpreserved Callee-Saved Caller-Saved R4-R11 R12
R14 (LR) R0-R3 R13 (SP) CPSR stack above SP stack below SP

20 Storing Saved Registers only on Stack
ARM Assembly Code ; R2 = result DIFFOFSUMS STR R4, [SP, #-4]! ; save R4 on stack ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 LDR R4, [SP], #4 ; restore R4 from stack MOV PC, LR ; return to caller

21 Storing Saved Registers only on Stack
ARM Assembly Code ; R2 = result DIFFOFSUMS STR R4, [SP, #-4]! ; save R4 on stack ADD R8, R0, R1 ; R8 = f + g ADD R9, R2, R3 ; R9 = h + i SUB R4, R8, R9 ; result = (f + g) - (h + i) MOV R0, R4 ; put return value in R0 LDR R4, [SP], #4 ; restore R4 from stack MOV PC, LR ; return to caller Notice code optimization for expanding/contracting stack

22 Nonleaf Function ARM Assembly Code
STR LR, [SP, #-4]! ; store LR on stack BL PROC2 ; call another function ... LDR LR, [SP], #4 ; restore LR from stack MOV PC, LR ; return to caller

23 Nonleaf Function Example
C Code int f1(int a, int b) { int i, x; x = (a + b)*(a − b); for (i=0; i<a; i++) x = x + f2(b+i); return x; } int f2(int p) { int r; r = p + 5; return r + p;

24 Nonleaf Function Example
C Code int f1(int a, int b) { int i, x; x = (a + b)*(a − b); for (i=0; i<a; i++) x = x + f2(b+i); return x; } int f2(int p) { int r; r = p + 5; return r + p; ARM Assembly Code ; R0=a, R1=b, R4=i, R5=x F1 PUSH {R4, R5, LR} ADD R5, R0, R1 SUB R12, R0, R1 MUL R5, R5, R12 MOV R4, #0 FOR CMP R4, R0 BGE RETURN PUSH {R0, R1} ADD R0, R1, R4 BL F2 ADD R5, R5, R0 POP {R0, R1} ADD R4, R4, #1 B FOR RETURN MOV R0, R5 POP {R4, R5, LR} MOV PC, LR ; R0=p, R4=r F2 PUSH {R4} ADD R4, R0, 5 ADD R0, R4, R0 POP {R4} MOV PC, LR

25 Nonleaf Function Example
ARM Assembly Code ; R0=a, R1=b, R4=i, R5=x F1 PUSH {R4, R5, LR} ; save regs ADD R5, R0, R1 ; x = (a+b) SUB R12, R0, R1 ; temp = (a-b) MUL R5, R5, R12 ; x = x*temp MOV R4, # ; i = 0 FOR CMP R4, R ; i < a? BGE RETURN ; no: exit loop PUSH {R0, R1} ; save regs ADD R0, R1, R4 ; arg is b+i BL F ; call f2(b+i) ADD R5, R5, R0 ; x = x+f2(b+i) POP {R0, R1} ; restore regs ADD R4, R4, #1 ; i++ B FOR ; repeat loop RETURN MOV R0, R ; return x POP {R4, R5, LR} ; restore regs MOV PC, LR ; return ; R0=p, R4=r F2 PUSH {R4} ; save regs ADD R4, R0, 5 ; r = p+5 ADD R0, R4, R0 ; return r+p POP {R4} ; restore regs MOV PC, LR ; return

26 Stack during Nonleaf Function
At beginning of f1 Just before calling f2 After calling f2

27 Recursive Function Call
C Code int factorial(int n) { if (n <= 1) return 1; else return (n * factorial(n-1)); }

28 Recursive Function Call
ARM Assembly Code 0x94 FACTORIAL STR R0, [SP, #-4]! ;store R0 on stack 0x STR LR, [SP, #-4]! ;store LR on stack 0x9C CMP R0, #2 ;set flags with R0-2 0xA BHS ELSE ;if (r0>=2) branch to else 0xA MOV R0, #1 ; otherwise return 1 0xA ADD SP, SP, #8 ; restore SP 1 0xAC MOV PC, LR ; return 0xB0 ELSE SUB R0, R0, #1 ; n = n - 1 0xB4 BL FACTORIAL ; recursive call 0xB LDR LR, [SP], #4 ; restore LR 0xBC LDR R1, [SP], #4 ; restore R0 (n) into R1 0xC MUL R0, R1, R0 ; R0 = n*factorial(n-1) 0xC MOV PC, LR ; return

29 Recursive Function Call
C Code int factorial(int n) { if (n <= 1) return 1; else return (n * factorial(n-1)); } ARM Assembly Code 0x94 FACTORIAL STR R0, [SP, #-4]! 0x STR LR, [SP, #-4]! 0x9C CMP R0, #2 0xA BHS ELSE 0xA MOV R0, #1 0xA ADD SP, SP, #8 0xAC MOV PC, LR 0xB0 ELSE SUB R0, R0, #1 0xB4 BL FACTORIAL 0xB LDR LR, [SP], #4 0xBC LDR R1, [SP], #4 0xC MUL R0, R1, R0 0xC MOV PC, LR

30 Stack during Recursive Call
Before call During call After call

31 Function Call Summary Caller Callee Puts arguments in R0-R3
Saves any needed registers (LR, maybe R0-R3, R8-R12) Calls function: BL CALLEE Restores registers Looks for result in R0 Callee Saves registers that might be disturbed (R4-R7) Performs function Puts result in R0 Returns: MOV PC, LR

32 How to Encode Instructions?

33 How to Encode Instructions?
Design Principle 1: Regularity supports design simplicity 32-bit data, 32-bit instructions For design simplicity, would prefer a single instruction format but…

34 How to Encode Instructions?
Design Principle 1: Regularity supports design simplicity 32-bit data, 32-bit instructions For design simplicity, would prefer a single instruction format but… Instructions have different needs

35 Design Principle 4 Good design demands good compromises
Multiple instruction formats allow flexibility ADD, SUB: use 3 register operands LDR, STR: use 2 register operands and a constant Number of instruction formats kept small to adhere to design principles 1 and 3 (regularity supports design simplicity and smaller is faster)

36 Machine Language Binary representation of instructions
Computers only understand 1’s and 0’s 32-bit instructions Simplicity favors regularity: 32-bit data & instructions 3 instruction formats: Data-processing Memory Branch

37 Instruction Formats Data-processing Memory Branch

38 Data-processing Instruction Format
Operands: Rn: first source register Src2: second source – register or immediate Rd: destination register Control fields: cond: specifies conditional execution op: the operation code or opcode funct: the function/operation to perform

39 Data-processing Control Fields
op = 002 for data-processing (DP) instructions funct is composed of cmd, I-bit, and S-bit

40 Data-processing Control Fields
op = 002 for data-processing (DP) instructions funct is composed of cmd, I-bit, and S-bit cmd: specifies the specific data-processing instruction. For example, cmd = for ADD cmd = for SUB I-bit I = 0: Src2 is a register I = 1: Src2 is an immediate S-bit: 1 if sets condition flags S = 0: SUB R0, R5, R7 S = 1: ADDS R8, R2, R4 or CMP R3, #10

41 Data-processing Src2 Variations
Src2 can be: Immediate Register Register-shifted register

42 Data-processing Src2 Variations
Src2 can be: Immediate Register Register-shifted register

43 Immediate Src2 Immediate encoded as:
imm8: 8-bit unsigned immediate rot: 4-bit rotation value 32-bit constant is: imm8 ROR (rot × 2)

44 Immediate Src2 Immediate encoded as:
imm8: 8-bit unsigned immediate rot: 4-bit rotation value 32-bit constant is: imm8 ROR (rot × 2) Example: imm8 = abcdefgh rot 32-bit constant 0000 abcd efgh 0001 gh ab cdef … 1111 ab cdef gh00

45 Immediate Src2 Immediate encoded as:
imm8: 8-bit unsigned immediate rot: 4-bit rotation value 32-bit constant is: imm8 ROR (rot × 2) Example: imm8 = abcdefgh ROR by X = ROL by (32-X) Ex: ROR by 30 = ROL by 2 rot 32-bit constant 0000 abcd efgh 0001 gh ab cdef … 1111 ab cdef gh00

46 DP Instruction with Immediate Src2
ADD R0, R1, #42 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (4) for ADD Src2 is an immediate so I = 1 Rd = 0, Rn = 1 imm8 = 42, rot = 0

47 DP Instruction with Immediate Src2
ADD R0, R1, #42 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (4) for ADD Src2 is an immediate so I = 1 Rd = 0, Rn = 1 imm8 = 42, rot = 0 0xE281002A

48 DP Instruction with Immediate Src2
SUB R2, R3, #0xFF0 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (2) for SUB Src2 is an immediate so I=1 Rd = 2, Rn = 3 imm8 = 0xFF imm8 must be rotated right by 28 to produce 0xFF0, so rot = 14 ROR by 28 = ROL by (32-28) = 4 0xE2432EFF

49 DP Instruction with Register Src2
Src2 can be: Immediate Register Register-shifted register

50 DP Instruction with Register Src2
Rm: the second source operand shamt5: the amount Rm is shifted sh: the type of shift (i.e., >>, <<, >>>, ROR)

51 DP Instruction with Register Src2
Rm: the second source operand shamt5: the amount Rm is shifted sh: the type of shift (i.e., >>, <<, >>>, ROR) First, consider unshifted versions of Rm (shamt5=0, sh=0)

52 DP Instruction with Register Src2
ADD R5, R6, R7 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (4) for ADD Src2 is a register so I=0 Rd = 5, Rn = 6, Rm = 7 shamt = 0, sh = 0 0xE

53 DP Instruction with Register Src2
Rm: the second source operand shamt5: the amount Rm is shifted sh: the type of shift Shift Type sh LSL 002 LSR 012 ASR 102 ROR 112 Now, consider shifted versions.

54 DP Instruction with Register Src2
ORR R9, R5, R3, LSR #2 Operation: R9 = R5 OR (R3 >> 2) cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (12) for ORR Src2 is a register so I=0 Rd = 9, Rn = 5, Rm = 3 shamt5 = 2, sh = 012 (LSR) 0xE

55 DP with Register-shifted Reg. Src2
Src2 can be: Immediate Register Register-shifted register

56 DP with Register-shifted Reg. Src2
EOR R8, R9, R10, ROR R12 Operation: R8 = R9 XOR (R10 ROR R12) cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (1) for EOR Src2 is a register so I=0 Rd = 8, Rn = 9, Rm = 10, Rs = 12 sh = 112 (ROR) 0xE0298C7A

57 Shift Instructions Encoding
Shift Type sh LSL 002 LSR 012 ASR 102 ROR 112

58 Shift Instructions: Immediate shamt
ROR R1, R2, #23 Operation: R1 = R2 ROR 23 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (13) for all shifts (LSL, LSR, ASR, and ROR) Src2 is an immediate-shifted register so I=0 Rd = 1, Rn = 0, Rm = 2 shamt5 = 23, sh = 112 (ROR) 0xE1A01BE2

59 Shift Instructions: Immediate shamt
ROR R1, R2, #23 Operation: R1 = R2 ROR 23 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (13) for all shifts (LSL, LSR, ASR, and ROR) Src2 is an immediate-shifted register so I=0 Rd = 1, Rn = 0, Rm = 2 shamt5 = 23, sh = 112 (ROR) Uses (immediate-shifted) register Src2 encoding 0xE1A01BE2

60 Shift Instructions: Register shamt
ASR R5, R6, R10 Operation: R5 = R6 >>> R107:0 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (13) for all shifts (LSL, LSR, ASR, and ROR) Src2 is a register so I=0 Rd = 5, Rn = 0, Rm = 6, Rs = 10 sh = 102 (ASR) 0xE1A05A56

61 Shift Instructions: Register shamt
ASR R5, R6, R10 Operation: R5 = R6 >>> R107:0 cond = (14) for unconditional execution op = 002 (0) for data-processing instructions cmd = (13) for all shifts (LSL, LSR, ASR, and ROR) Src2 is a register so I=0 Rd = 5, Rn = 0, Rm = 6, Rs = 10 sh = 102 (ASR) Uses register-shifted register Src2 encoding 0xE1A05A56

62 Review: Data-processing Format
Src2 can be: Immediate Register Register-shifted register

63 Instruction Formats Data-processing Memory Branch

64 Memory Instruction Format
Encodes: LDR, STR, LDRB, STRB op = 012 Rn = base register Rd = destination (load), source (store) Src2 = offset funct = 6 control bits

65 Offset Options Recall: Address = Base Address + Offset
Example: LDR R1, [R2, #4] Base Address = R2, Offset = 4 Address = (R2 + 4) Base address always in a register The offset can be: an immediate a register or a scaled (shifted) register

66 Offset Examples ARM Assembly Memory Address R3 + 4 R5 – 16 R6 + R7
LDR R0, [R3, #4] R3 + 4 LDR R0, [R5, #-16] R5 – 16 LDR R1, [R6, R7] R6 + R7 LDR R2, [R8, -R9] R8 – R9 LDR R3, [R10, R11, LSL #2] R10 + (R11 << 2) LDR R4, [R1, -R12, ASR #4] R1 – (R12 >>> 4) LDR R0, [R9] R9

67 Memory Instruction Format
Encodes: LDR, STR, LDRB, STRB op = 012 Rn = base register Rd = destination (load), source (store) Src2 = offset: register (optionally shifted) or immediate funct = 6 control bits

68 Indexing Modes Mode Address Base Reg. Update Examples Offset
Base register ± Offset No change Preindex Postindex Base register Examples Offset: LDR R1, [R2, #4] ; R1 = mem[R2+4] Preindex: LDR R3, [R5, #16]! ; R3 = mem[R5+16] ; R5 = R5 + 16 Postindex: LDR R8, [R1], #8 ; R8 = mem[R1] ; R1 = R1 + 8

69 Memory Instruction Format
funct: I: Immediate bar P: Preindex U: Add B: Byte W: Writeback L: Load

70 Memory Format funct Encodings
Type of Operation L B Instruction STR 1 STRB LDR LDRB

71 Memory Format funct Encodings
Type of Operation Indexing Mode L B Instruction STR 1 STRB LDR LDRB P W Indexing Mode 1 Not supported Postindex Offset Preindex

72 Memory Format funct Encodings
Type of Operation Indexing Mode L B Instruction STR 1 STRB LDR LDRB P W Indexing Mode 1 Not supported Postindex Offset Preindex Add/Subtract Immediate/Register Offset Value I U Immediate offset in Src2 Subtract offset from base 1 Register offset in Src2 Add offset to base

73 Memory Instruction Format
Encodes: LDR, STR, LDRB, STRB op = 012 Rn = base register Rd = destination (load), source (store) Src2 = offset: immediate or register (optionally shifted) funct = I (immediate bar), P (preindex), U (add), B (byte), W (writeback), L (load)

74 Memory Instr. with Immediate Src2
STR R11, [R5], #-26 Operation: mem[R5] <= R11; R5 = R5 - 26 cond = (14) for unconditional execution op = 012 (1) for memory instruction funct = (0) I = 0 (immediate offset), P = 0 (postindex), U = 0 (subtract), B = 0 (store word), W = 0 (postindex), L = 0 (store) Rd = 11, Rn = 5, imm12 = 26

75 Memory Instr. with Register Src2
LDR R3, [R4, R5] Operation: R3 <= mem[R4 + R5] cond = (14) for unconditional execution op = 012 (1) for memory instruction funct = (57) I = 1 (register offset), P = 1 (offset indexing), U = 1 (add), B = 0 (load word), W = 0 (offset indexing), L = 1 (load) Rd = 3, Rn = 4, Rm = 5 (shamt5 = 0, sh = 0) = 0xE

76 Memory Instr. with Scaled Reg. Src2
STR R9, [R1, R3, LSL #2] Operation: mem[R1 + (R3 << 2)] <= R9 cond = (14) for unconditional execution op = 012 (1) for memory instruction funct = (0) I = 1 (register offset), P = 1 (offset indexing), U = 1 (add), B = 0 (store word), W = 0 (offset indexing), L = 0 (store) Rd = 9, Rn = 1, Rm = 3, shamt = 2, sh = 002 (LSL) = 0xE

77 Review: Memory Instruction Format
Encodes: LDR, STR, LDRB, STRB op = 012 Rn = base register Rd = destination (load), source (store) Src2 = offset: register (optionally shifted) or immediate funct = I (immediate bar), P (preindex), U (add), B (byte), W (writeback), L (load)

78 Instruction Formats Data-processing Memory Branch

79 Branch Instruction Format
Encodes B and BL op = 102 imm24: 24-bit immediate funct = 1L2: L = 1 for BL, L = 0 for B

80 Encoding Branch Target Address
Branch Target Address (BTA): Next PC when branch taken BTA is relative to current PC + 8 imm24 encodes BTA imm24 = # of words BTA is away from PC+8

81 Branch Instruction: Example 1
ARM assembly code 0xA BLT THERE 0xA4 ADD R0, R1, R2 0xA SUB R0, R0, R9 0xAC ADD SP, SP, #8 0xB MOV PC, LR 0xB4 THERE SUB R0, R0, #1 0xB8 BL TEST PC PC = 0xA0 PC + 8 = 0xA8 THERE label is 3 instructions past PC+8 So, imm24 = 3 PC+8 BTA 0xBA000003

82 Branch Instruction: Example 2
ARM assembly code 0x8040 TEST LDRB R5, [R0, R3] 0x8044 STRB R5, [R1, R3] 0x8048 ADD R3, R3, #1 0x8044 MOV PC, LR 0x8050 BL TEST 0x8054 LDR R3, [R1], #4 0x8058 SUB R4, R3, #9 BTA PC = 0x8050 PC + 8 = 0x8058 TEST label is 6 instructions before PC+8 So, imm24 = -6 PC PC+8 0xEBFFFFFA

83 Review: Instruction Formats

84 Conditional Execution
Encode in cond bits of machine instruction For example, ANDEQ R1, R2, R3 (cond = 0000) ORRMI R4, R5, #0xF (cond = 0100) SUBLT R9, R3, R8 (cond = 1011)

85 Review: Condition Mnemonics

86 Conditional Execution: Machine Code

87 Interpreting Machine Code
Start with op: tells how to parse rest op = 00 (Data-processing) op = 01 (Memory) op = 10 (Branch) I-bit: tells how to parse Src2 Data-processing instructions: If I-bit is 0, bit 4 determines if Src2 is a register (bit 4 = 0) or a register-shifted register (bit 4 = 1) Memory instructions: Examine funct bits for indexing mode, instruction, and add or subtract offset

88 Interpreting Machine Code: Example 1
0xE

89 Interpreting Machine Code: Example 1
0xE Start with op: 002, so data-processing instruction

90 Interpreting Machine Code: Example 1
0xE Start with op: 002, so data-processing instruction I-bit: 0, so Src2 is a register bit 4: 0, so Src2 is a register (optionally shifted by shamt5)

91 Interpreting Machine Code: Example 1
0xE Start with op: 002, so data-processing instruction I-bit: 0, so Src2 is a register bit 4: 0, so Src2 is a register (optionally shifted by shamt5) cmd: (2), so SUB Rn=7, Rd=5, Rm=1, shamt5 = 0, sh = 0 So, instruction is: SUB R5,R7,R1

92 Interpreting Machine Code: Example 2
0xE

93 Interpreting Machine Code: Example 2
0xE Start with op: 012, so memory instruction funct: B=0, L=1, so LDR; P=1, W=0, so offset indexing; I=0, so immediate offset, U=1, so add offset Rn=4, Rd=9, imm12 = 16 So, instruction is: LDR R9,[R4,#16]

94 Addressing Modes How do we address operands? Register Immediate Base
PC-Relative

95 Addressing Modes How do we address operands? Register Only Immediate
Base PC-Relative

96 Register Addressing Source and destination operands found in registers
Used by data-processing instructions Three submodes: Register-only Immediate-shifted register Register-shifted register

97 Register Addressing Examples
Register-only Example: ADD R0, R2, R7 Immediate-shifted register Example: ORR R5, R1, R3, LSL #1 Register-shifted register Example: SUB R12, R9, R0, ASR R1

98 Addressing Modes How do we address operands? Register Only Immediate
Base PC-Relative

99 Immediate Addressing Operands found in registers and immediates
Example: ADD R9, R1, #14 Uses data-processing format with I=1 Immediate is encoded as 8-bit immediate (imm8) 4-bit rotation (rot) 32-bit immediate = imm8 ROR (rot x 2)

100 Addressing Modes How do we address operands? Register Only Immediate
Base PC-Relative

101 Base Addressing Address of operand is: base register + offset
Offset can be a: 12-bit Immediate Register Immediate-shifted Register

102 Base Addressing Examples
Immediate offset Example: LDR R0, [R8, #-11] (R0 = mem[R8 - 11] ) Register offset Example: LDR R1, [R7, R9] (R1 = mem[R7 + R9] ) Immediate-shifted register offset Example: STR R5, [R3, R2, LSL #4] (R5 = mem[R3 + (R2 << 4)] )

103 Addressing Modes How do we address operands? Register Only Immediate
Base PC-Relative

104 PC-Relative Addressing
Used for branches Branch instruction format: Operands are PC and a signed 24-bit immediate (imm24) Changes the PC New PC is relative to the old PC imm24 indicates the number of words away from PC+8 PC = (PC+8) + (SignExtended(imm24) x 4)

105 Power of the Stored Program
32-bit instructions & data stored in memory Sequence of instructions: only difference between two applications To run a new program: No rewiring required Simply store new program in memory Program Execution: Processor fetches (reads) instructions from memory in sequence Processor performs the specified operation

106 The Stored Program Program Counter (PC): keeps track of current instruction

107 Up Next How to implement the ARM Instruction Set
Architecture in Hardware Microarchitecture